Xilinx ISEをコマンドラインで使う

　最初はGUIでやってみて、どういうコマンドが実行されたかがcmd_logという拡張子のファイルに保存されるので、それを見てMakefileを書くのが良いかな。
　ここには書いていないけれども、ファイルの依存関係も書くと便利だと思う。
　今回のものはSynplify Premierを使っているので、それ向けになってる。Xilinxのツールだとxstだったかな。それぞれのコマンドの引数は-helpなどで出るのでそれを参考にするとか。

　とりあえずのサンプルとして。後で追記予定。

# Makefile sample
#
# usage :
#  make all	- synthesis
#  make clean	- clean up log, compiled files

CUR_DIR			= .

DESIGN			= hoge
DEVICE			= xc3s400-tq144-4 

XILINX_PATH		= $(subst \,/,$(XILINX)/bin/nt)

ifeq ($(SYNPLICITY),)
SYNPLICITY_BIN		= synplify_premier.exe
else
SYNPLICITY_BIN		= $(SYNPLICITY)
endif
SYNPLICITY_LICENSE	= synplifypremierdp

COREGEN_DIR		= ../coregen

PACK_FILE		= $(DESIGN)$(shell date +%y%m%d).tar.gz
PACK_LIST		= pack_list

CONF_FILE		= \
			$(DESIGN).prd \
			$(DESIGN).prj \
			$(DESIGN).sdc

OTHER_FILE		= \
			$(shell ls rpt*) \
			Makefile

CLEAN_FILE_LIST		= \
			_impactbatch.log \
			$(DESIGN).bld \
			$(DESIGN).data \
			$(DESIGN).edf \
			$(DESIGN).fse \
			$(DESIGN).gyd \
			$(DESIGN).htm \
			$(DESIGN).jed \
			$(DESIGN).map \
			$(DESIGN).mfd \
			$(DESIGN).mod \
			$(DESIGN).ncf \
			$(DESIGN).nga \
			$(DESIGN).ngd \
			$(DESIGN).pad\
			$(DESIGN).pnx \
			$(DESIGN).rpt \
			$(DESIGN).sap \
			$(DESIGN).srd \
			$(DESIGN).srm \
			$(DESIGN).srr \
			$(DESIGN).srs \
			$(DESIGN).szr \
			$(DESIGN).tlg \
			$(DESIGN).tspec \
			$(DESIGN).vm6 \
			$(DESIGN).xml \
			$(DESIGN)_build.xml \
			$(DESIGN)_pad.csv\
			rpt_$(DESIGN).areasrr \
			rpt_$(DESIGN)_areasrr.htm\
			run_options.txt \
			stdout.log \
			timing_report.htm \
			tmperr.err

CLEAN_DIR_LIST		= \
			$(DESIGN)_html \
			backup \
			syntmp \
			verif \
			_ngo

all: top

top: synthesis translate map par report

# build edf file
synthesis:
	$(SYNPLICITY_BIN) -licensetype $(SYNPLICITY_LICENSE) -batch $(DESIGN).prj

# build ngd file
translate:
	$(XILINX_PATH)/ngdbuild -verbose -quiet -i -dd _ngo -sd $(COREGEN_DIR) -nt timestamp -p $(DEVICE) $(DESIGN).edf $(DESIGN).ngd

# exec mapper
map:
	$(XILINX_PATH)/map -p $(DEVICE) -cm area -pr b -k 4 -c 100 -o $(DESIGN)_map.ncd $(DESIGN).ngd $(DESIGN).pcf

# exec place and route
par:
	$(XILINX_PATH)/par -w -ol std -t 1 $(DESIGN)_map.ncd $(DESIGN).ncd $(DESIGN).pcf

# build report file
report:
	$(XILINX_PATH)/trce -e 3 -s 4 -xml $(DESIGN) $(DESIGN).ncd -o $(DESIGN).twr $(DESIGN).pcf

# build bit file
bitgen:
	$(XILINX_PATH)/bitgen -m -f $(DESIGN).ut $(DESIGN).ncd $(DESIGN) $(DESIGN).pcf

# build mcs file
promgen:
	$(XILINX_PATH)/promgen -w -p mcs -c FF -o ./$(DESIGN).mcs -u 0 ./$(DESIGN).bit -x $(CONF_DEVICE)

clean:
	rm -f $(PACK_LIST) $(CLEAN_FILE_LIST)
	rm -Rf $(CLEAN_DIR_LIST)

# pack source etc.
$(PACK_LIST)::
	@for file in $(CONF_FILE) \
		$(OTHER_FILE); do \
		if [ -f $$file ]; then \
			echo $(CUR_DIR)/$$file; \
		fi \
	done

pack::
	@rm -f $(PACK_LIST)
	make -s $(PACK_LIST) -e CUR_DIR=$(CUR_DIR) pack_list > $(PACK_LIST)
	tar cfh - `cat $(PACK_LIST)` |gzip > $(PACK_FILE)
	@rm -f $(PACK_LIST)

pack_check::
	gzip -d < $(PACK_FILE) |tar tvf -
	ls -l $(PACK_FILE)